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CODES
2003
IEEE
14 years 25 days ago
A codesigned on-chip logic minimizer
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
Roman L. Lysecky, Frank Vahid
JPDC
2008
108views more  JPDC 2008»
13 years 7 months ago
Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP
Energy saving is becoming one of the major design issues in processor architectures with multiple functional units (FUs). Nested loops are usually the most critical part in multim...
Meikang Qiu, Edwin Hsing-Mean Sha, Meilin Liu, Man...
CF
2005
ACM
13 years 9 months ago
Drowsy region-based caches: minimizing both dynamic and static power dissipation
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
MIS
1999
Springer
84views Multimedia» more  MIS 1999»
13 years 11 months ago
Minimizing Bandwidth Requirements for On-Demand Data Delivery
Recent techniques for multicast or broadcast delivery of streaming media can provide immediate service to each client request yet achieve considerable client stream sharing (i.e.,...
Derek L. Eager, Mary K. Vernon, John Zahorjan
DAC
2004
ACM
13 years 11 months ago
A methodology to improve timing yield in the presence of process variations
The ability to control the variations in IC fabrication process is rapidly diminishing as feature sizes continue towards the sub-100 nm regime. As a result, there is an increasing...
Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wa...