72 search results - page 4 / 15 » Timing Optimization of Logic Network Using Gate Duplication |
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Ignoring the effect of simultaneous switching for logic gates causes silicon failures for high performance microprocessor designs. The main reason to omit this effect is the run...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
DATE
2010
IEEE
14 years 17 days ago
2010
IEEE
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...