72 search results - page 6 / 15 » Timing Optimization of Logic Network Using Gate Duplication |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
MEMICS
2010
13 years 2 months ago
2010
Recently, almost uncontrolled technological progress allows so called high-throughput data collection for sophisticated and complex experimental biological systems analysis. Espec...
BROADNETS
2005
IEEE
14 years 1 months ago
2005
IEEE
—The peer-to-peer technology offers many advantages, but at the same time, it poses many novel challenges for the research community. Modern peer-to-peer systems are characterize...