290 search results - page 34 / 58 » Timing analysis in high-level synthesis |
PG
2007
IEEE
14 years 4 months ago
2007
IEEE
Interactive animation systems often use a level-of-detail (LOD) control to reduce the computational cost by eliminating unperceivable details of the scene. Most methods employ a m...
LCPC
2001
Springer
14 years 2 months ago
2001
Springer
Abstract. The DEFACTO project - a Design Environment For Adaptive Computing TechnOlogy - is a system that maps computations, expressed in high-level languages such as C, directly o...
ISPD
2003
ACM
14 years 3 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
CODES
2005
IEEE
14 years 3 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
BROADNETS
2005
IEEE
14 years 3 months ago
2005
IEEE
—In this paper, we present an extended Mobile Backbone Network (MBN) topology synthesis algorithm (ETSA) for constructing and maintaining a dynamic backbone structure in mobile w...