184 search results - page 3 / 37 » Timing budgeting under arbitrary process variations |
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
With the emerging process variations in fabrication, the traditional corner-based timing optimization techniques become prohibitive. Buffer insertion is a very useful technique fo...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
With the ever-increasing transistor variability in CMOS technology, it is essential to integrate variation-aware performance analysis into the task allocation and scheduling proce...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— We present a new linear time technique to compute criticality information in a timing graph by dividing it into “zones”. Errors in using tightness probabilities for critica...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a ...