53 search results - page 5 / 11 » Timing driven maze routing |
ISPD
2009
ACM
14 years 3 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
ECRTS
2004
IEEE
14 years 21 days ago
2004
IEEE
We present an approach to partitioning and mapping for multicluster embedded systems consisting of time-triggered and eventtriggered clusters, interconnected via gateways. We have...
FPGA
1998
ACM
14 years 1 months ago
1998
ACM
Three factors are driving the demand for rapid FPGA compilation. First, as FPGAs have grown in logic capacity, the compile computation has grown more quickly than the compute powe...
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
DAC
2006
ACM
14 years 10 months ago
2006
ACM
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...