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VLSID
2003
IEEE
103views VLSI» more  VLSID 2003»
14 years 9 months ago
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
CODES
2006
IEEE
14 years 2 months ago
Floorplan driven leakage power aware IP-based SoC design space exploration
Multi-million gate System-on-Chip (SoC) designs increasingly rely on Intellectual Property (IP) blocks. However, due to technology scaling the leakage power consumption of the IP ...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
MICRO
2003
IEEE
143views Hardware» more  MICRO 2003»
14 years 1 months ago
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik ...
DATE
1999
IEEE
112views Hardware» more  DATE 1999»
14 years 28 days ago
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will...
Markus Bühler, Matthias Papesch, K. Kapp, Utz...
ECRTS
2004
IEEE
14 years 10 days ago
Energy-Efficient Policies for Request-Driven Soft Real-Time Systems
Computing systems, ranging from small battery-operated embedded systems to more complex general purpose systems, are designed to satisfy various computation demands in some accept...
Cosmin Rusu, Ruibin Xu, Rami G. Melhem, Daniel Mos...