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ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
14 years 18 days ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...
ISPDC
2003
IEEE
14 years 1 months ago
Hardware-based Power Management for Real-Time Applications
— This paper presents a new power management technique integrated into a multithreaded microcontroller with builtin real-time scheduling schemes. Power management is done by hard...
Sascha Uhrig, Theo Ungerer
DAC
2008
ACM
13 years 10 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik
DATE
2010
IEEE
134views Hardware» more  DATE 2010»
13 years 7 months ago
Combining optimizations in automated low power design
—Starting from sequential programs, we present an approach combining data reuse, multi-level MapReduce, and pipelining to automatically find the most power-efficient designs th...
Qiang Liu, Tim Todman, Wayne Luk
EUC
2004
Springer
14 years 2 months ago
Power-Aware Scheduling of Mixed Task Sets in Priority-Driven Systems
We propose power-aware on-line task scheduling algorithms for mixed task sets which consist of both periodic and aperiodic tasks. The proposed algorithms utilize the execution beha...
Dongkun Shin, Jihong Kim