Sciweavers

264 search results - page 17 / 53
» Timing driven power gating
Sort
View
ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
14 years 2 months ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
ICCAD
2008
IEEE
117views Hardware» more  ICCAD 2008»
14 years 3 months ago
A novel sequential circuit optimization with clock gating logic
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang
TASLP
2008
104views more  TASLP 2008»
13 years 8 months ago
Tracking of Nonstationary Noise Based on Data-Driven Recursive Noise Power Estimation
This paper considers estimation of the noise spectral variance from speech signals contaminated by highly nonstationary noise sources. The method can accurately track fast changes ...
Jan S. Erkelens, Richard Heusdens
ISCAS
2008
IEEE
115views Hardware» more  ISCAS 2008»
14 years 3 months ago
FSMD partitioning for low power using simulated annealing
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...
Nainesh Agarwal, Nikitas J. Dimopoulos
ASPDAC
2008
ACM
122views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Total power optimization combining placement, sizing and multi-Vt through slack distribution management
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
Tao Luo, David Newmark, David Z. Pan