264 search results - page 19 / 53 » Timing driven power gating |
GLVLSI
2010
IEEE
13 years 10 months ago
2010
IEEE
In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorith...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
VLSID
2007
IEEE
14 years 9 months ago
2007
IEEE
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
— In this paper we propose a new metric called “effective tunneling capacitance” (Ct eff ) to quantify the transient swing in the gate leakage (gate oxide tunneling) current ...
ICCD
2004
IEEE
14 years 5 months ago
2004
IEEE
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progress...