264 search results - page 3 / 53 » Timing driven power gating |
ISLPED
2009
ACM
14 years 3 months ago
2009
ACM
Power gating is usually driven by a predictive control, and frequent mispredictions can counter-productively lead to a large increase in energy consumption. This energy vulnerabil...
PATMOS
2005
Springer
14 years 2 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
FPL
2009
Springer
14 years 1 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
ICCD
2006
IEEE
14 years 5 months ago
2006
IEEE
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
ICCD
2008
IEEE
14 years 5 months ago
2008
IEEE
—IR drop noise has become a critical issue in advanced process technologies. Traditionally, timing analysis in which the IR drop noise is considered assumes a worst-case IR drop ...