264 search results - page 7 / 53 » Timing driven power gating |
DAC
2002
ACM
14 years 9 months ago
2002
ACM
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
ISVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
TCAD
2008
13 years 8 months ago
2008
Abstract--Design of a suitable power gating (e.g., multithreshold CMOS or super cutoff CMOS) structure is an important and challenging task in sub-90nm VLSI circuits where leakage ...
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Publication
With the technology moving into the deep sub-100nm region, the increase of leakage power consumption necessitates more aggressive power reduction techniques. Power gating is a prom...