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ASYNC
2007
IEEE
132views Hardware» more  ASYNC 2007»
14 years 1 months ago
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
SBCCI
2003
ACM
160views VLSI» more  SBCCI 2003»
14 years 18 days ago
Novel Design Methodology for High-Performance XOR-XNOR Circuit Design
As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequen...
Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi
ICCAD
2006
IEEE
123views Hardware» more  ICCAD 2006»
14 years 4 months ago
A revisit to floorplan optimization by Lagrangian relaxation
With the advent of deep sub-micron (DSM) era, floorplanning has become increasingly important in physical design process. In this paper we clarify a misunderstanding in using Lag...
Chuan Lin, Hai Zhou, Chris C. N. Chu
ICCAD
2000
IEEE
109views Hardware» more  ICCAD 2000»
13 years 11 months ago
Latency-Guided On-Chip Bus Network Design
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
Milenko Drinic, Darko Kirovski, Seapahn Meguerdich...
ICCAD
2003
IEEE
145views Hardware» more  ICCAD 2003»
14 years 4 months ago
Manufacturing-Aware Physical Design
Ultra-deep submicron manufacturability impacts physical design (PD) through complex layout rules and large guardbands for process variability; this creates new requirements for ne...
Puneet Gupta, Andrew B. Kahng