4164 search results - page 16 / 833 » Timing model reduction for hierarchical timing analysis |
DAC
2003
ACM
14 years 2 months ago
2003
ACM
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
ICCD
2001
IEEE
14 years 5 months ago
2001
IEEE
Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2GHz has caused crosstalk noise to become a serious problem, that degr...
BMCBI
2011
13 years 17 days ago
2011
Background: The analysis of gene expression from time series underpins many biological studies. Two basic forms of analysis recur for data of this type: removing inactive (quiet) ...
SIGMETRICS
2002
ACM
13 years 8 months ago
2002
ACM
As processor microarchitectures continue to increase in complexity, so does the time required to explore the design space. Performing cycle
AAIM
2009
Springer
14 years 3 months ago
2009
Springer
During the last years, a wide range of huge networks has been made available to researchers. The discovery of natural groups, a task called graph clustering, in such datasets is a ...