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» Timing-driven optimization using lookahead logic circuits
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DATE
2009
IEEE
107views Hardware» more  DATE 2009»
14 years 2 months ago
Sequential logic rectifications with approximate SPFDs
In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential ci...
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, R...
DATE
2006
IEEE
140views Hardware» more  DATE 2006»
14 years 4 months ago
Optimization of regular expression pattern matching circuits on FPGA
Regular expressions are widely used in Network Intrusion Detection System (NIDS) to represent patterns of network attacks. Since traditional software-only NIDS cannot catch up to ...
Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang,...
FCCM
2006
IEEE
162views VLSI» more  FCCM 2006»
14 years 4 months ago
Power Visualization, Analysis, and Optimization Tools for FPGAs
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...
Matthew French, Li Wang, Michael J. Wirthlin
ICCAD
2007
IEEE
139views Hardware» more  ICCAD 2007»
14 years 4 months ago
Using functional independence conditions to optimize the performance of latency-insensitive systems
—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...
Cheng-Hong Li, Luca P. Carloni
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
14 years 7 months ago
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram