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» Timing-driven optimization using lookahead logic circuits
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DAC
2004
ACM
14 years 8 months ago
Leakage-and crosstalk-aware bus encoding for total power reduction
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
Harmander Deogun, Rajeev R. Rao, Dennis Sylvester,...
DAC
2010
ACM
13 years 10 months ago
Efficient fault simulation on many-core processors
Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structure...
Michael A. Kochte, Marcel Schaal, Hans-Joachim Wun...
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
Swaroop Ghosh, Kaushik Roy
CPAIOR
2007
Springer
14 years 1 months ago
Cost-Bounded Binary Decision Diagrams for 0-1 Programming
Abstract. In recent work binary decision diagrams (BDDs) were introduced as a technique for postoptimality analysis for integer programming. In this paper we show that much smaller...
Tarik Hadzic, John N. Hooker
ISLPED
2004
ACM
102views Hardware» more  ISLPED 2004»
14 years 13 days ago
Microarchitectural power modeling techniques for deep sub-micron microprocessors
The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance h...
Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M...