188 search results - page 9 / 38 » Timing-driven optimization using lookahead logic circuits |
GECCO
2007
Springer
14 years 4 months ago
2007
Springer
This paper shows that the evolutionary design of digital circuits which is conducted at the gate level is able to produce human-competitive circuits at the transistor level. In ad...
DAC
1996
ACM
14 years 2 months ago
1996
ACM
Technology mapping requires the unmapped logic network to be represented in terms of base functions, usually two-input NORs and inverters. Technology decomposition is the step tha...
AHS
2006
IEEE
14 years 1 months ago
2006
IEEE
The following article describes and discusses the suitability of the particle swarm optimization (PSO) for the employment with blind adaptation of the directional characteristic o...
ISLPED
2004
ACM
14 years 3 months ago
2004
ACM
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
DAC
1994
ACM
14 years 2 months ago
1994
ACM
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circui...