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CASES
2008
ACM
15 years 4 months ago
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
Houman Homayoun, Mohammad A. Makhzan, Alexander V....
112
Voted
ICDCS
2010
IEEE
15 years 4 months ago
CacheCast: Eliminating Redundant Link Traffic for Single Source Multiple Destination Transfers
Due to the lack of multicast services in the Internet, applications based on single source multiple destinations transfers such as video conferencing, IP radio, IPTV must use unica...
Piotr Srebrny, Thomas Plagemann, Vera Goebel, Andr...
114
Voted
ISCA
2009
IEEE
276views Hardware» more  ISCA 2009»
15 years 9 months ago
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Many multi-core processors employ a large last-level cache (LLC) shared among the multiple cores. Past research has demonstrated that sharing-oblivious cache management policies (...
Yuejian Xie, Gabriel H. Loh
134
Voted
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
15 years 6 months ago
Low Static-Power Frequent-Value Data Caches
: Static energy dissipation in cache memories will constitute an increasingly larger portion of total microprocessor energy dissipation due to nanoscale technology characteristics ...
Chuanjun Zhang, Jun Yang 0002, Frank Vahid
IMS
2000
125views Hardware» more  IMS 2000»
15 years 6 months ago
Compiler-Directed Cache Line Size Adaptivity
The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size tha...
Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbau...