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» Towards Nanoelectronics Processor Architectures
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DAC
2009
ACM
14 years 8 months ago
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
ICCD
2008
IEEE
126views Hardware» more  ICCD 2008»
14 years 2 months ago
Accelerating search and recognition with a TCAM functional unit
Abstract— World data is increasing rapidly, doubling almost every three years[1][2]. To comprehend and use this data effectively, search and recognition (SR) applications will de...
Atif Hashmi, Mikko Lipasti
TC
2011
13 years 2 months ago
StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs
—CMOS scaling has long been a source of dramatic performance gains. However, semiconductor feature size reduction has resulted in increasing levels of operating temperatures and ...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
HPCA
2002
IEEE
14 years 8 months ago
Quantifying Load Stream Behavior
The increasing performance gap between processors and memory will force future architectures to devote significant resources towards removing and hiding memory latency. The two ma...
Suleyman Sair, Timothy Sherwood, Brad Calder
FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
14 years 28 days ago
In-system FPGA prototyping of an itanium microarchitecture
We describe an effort to prototype an Itanium microarchitecture using an FPGA. The microarchitecture model is written in the Bluespec hardware description language (HDL) and suppo...
Roland E. Wunderlich, James C. Hoe