513 search results - page 90 / 103 » Towards a Model for Hardware and Software Functional Partiti... |
ISCA
2000
IEEE
14 years 24 days ago
2000
IEEE
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
MICRO
2010
IEEE
13 years 6 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
CODES
1999
IEEE
14 years 22 days ago
1999
IEEE
o much higher levels of abstraction than today's design practices, which are usually at the level of synthesizable RTL for custom hardware or Instruction Set Simulator (ISS) f...
EUROSYS
2008
ACM
14 years 5 months ago
2008
ACM
The continuing frequency and seriousness of security incidents underlines the importance of application security. Decentralized information flow control (DIFC), a promising tool ...