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ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
14 years 1 months ago
Validation in a Component-Based Design Flow for Multicore SoCs
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima,...
HPCA
2011
IEEE
13 years 6 days ago
Dynamic parallelization of JavaScript applications using an ultra-lightweight speculation mechanism
As the web becomes the platform of choice for execution of more complex applications, a growing portion of computation is handed off by developers to the client side to reduce net...
Mojtaba Mehrara, Po-Chun Hsu, Mehrzad Samadi, Scot...
HPCA
2009
IEEE
14 years 9 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
HPDC
2012
IEEE
11 years 11 months ago
Dynamic adaptive virtual core mapping to improve power, energy, and performance in multi-socket multicores
Consider a multithreaded parallel application running inside a multicore virtual machine context that is itself hosted on a multi-socket multicore physical machine. How should the...
Chang Bae, Lei Xia, Peter A. Dinda, John R. Lange
CASES
2006
ACM
14 years 2 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh