Today’s software developments are faced with steadily increasing expectations: software has to be developed faster, better, and cheaper. At the same time, application complexity ...
Klaus-Dieter Althoff, Andreas Birk, Susanne Hartko...
In a VHDL-based design flow for applicationspecific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Sta...
Josef Fleischmann, Rolf Schlagenhaft, Martin Pelle...
In this paper, our memory architecture exploration methodology and CAD techniques for network protocol applications are presented. Prototype tools have been implemented, and appli...
Peter Slock, Sven Wuytack, Francky Catthoor, Gjalt...
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
The paper presents in brief a project aimed at the development of a methodology and corresponding software tools intended for building of proper environments giving up means for s...
Maria Nisheva-Pavlova, Pavel Pavlov, Nikolay Marko...