Sciweavers

93 search results - page 14 / 19
» Transactional Memory: Architectural Support for Lock-Free Da...
Sort
View
ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
14 years 1 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
14 years 1 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
SAC
2006
ACM
14 years 1 months ago
Supporting transparent model update in distributed CASE tool integration
Model Driven Architecture (MDA) is a software development approach that focuses on models. In order to support MDA, a lot of CASE tools have emerged; each of them provides a diffe...
Prawee Sriplakich, Xavier Blanc, Marie-Pierre Gerv...
VLDB
1987
ACM
93views Database» more  VLDB 1987»
13 years 11 months ago
FAD, a Powerful and Simple Database Language
FAD is a powerful and simple language designed for a highly parallel database machine. The basic concepts of the language are its data structures (which we call objects) and its p...
François Bancilhon, Ted Briggs, Setrag Khos...
CODES
2005
IEEE
14 years 1 months ago
Enhancing security through hardware-assisted run-time validation of program data properties
The growing number of information security breaches in electronic and computing systems calls for new design paradigms that consider security as a primary design objective. This i...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...