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» Trusted Design in FPGAs
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FPGA
2009
ACM
188views FPGA» more  FPGA 2009»
14 years 2 months ago
Clock power reduction for virtex-5 FPGAs
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Qiang Wang, Subodh Gupta, Jason Helge Anderson
FPGA
2005
ACM
137views FPGA» more  FPGA 2005»
14 years 28 days ago
HARP: hard-wired routing pattern FPGAs
Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configur...
Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia...
FPGA
2006
ACM
155views FPGA» more  FPGA 2006»
13 years 11 months ago
Improvements to technology mapping for LUT-based FPGAs
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
ICCAD
2001
IEEE
103views Hardware» more  ICCAD 2001»
14 years 4 months ago
Interconnect Resource-Aware Placement for Hierarchical FPGAs
In this paper, we utilize Rent’s rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design c...
Amit Singh, Ganapathy Parthasarathy, Malgorzata Ma...
FPGA
2006
ACM
93views FPGA» more  FPGA 2006»
13 years 11 months ago
Measuring the gap between FPGAs and ASICs
This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power cons...
Ian Kuon, Jonathan Rose