524 search results - page 14 / 105 » Two efficient methods to reduce power and testing time |
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
VLDB
2007
ACM
14 years 8 months ago
2007
ACM
Similarity-based search over time-series databases has been a hot research topic for a long history, which is widely used in many applications, including multimedia retrieval, dat...
ISQED
2003
IEEE
14 years 1 months ago
2003
IEEE
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
ICCD
2008
IEEE
14 years 5 months ago
2008
IEEE
— The aggregate power consumption of the Internet is increasing at an alarming rate, due in part to the rapid increase in the number of connected edge devices such as desktop PCs...