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» Two efficient methods to reduce power and testing time
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TC
2008
15 years 4 months ago
Exploiting In-Memory and On-Disk Redundancy to Conserve Energy in Storage Systems
Abstract--Today's storage systems place an imperative demand on energy efficiency. A storage system often places single-rotationrate disks into standby mode by stopping them f...
Jun Wang, Xiaoyu Yao, Huijun Zhu
DAC
2006
ACM
16 years 5 months ago
Charge recycling in MTCMOS circuits: concept and analysis
Designing an energy efficient power gating structure is an important and challenging task in Multi-Threshold CMOS (MTCMOS) circuit design. In order to achieve a very low power des...
Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram
VTS
2007
IEEE
129views Hardware» more  VTS 2007»
15 years 10 months ago
Supply Voltage Noise Aware ATPG for Transition Delay Faults
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
UIST
2003
ACM
15 years 9 months ago
Considering the direction of cursor movement for efficient traversal of cascading menus
Cascading menus are commonly seen in most GUI systems. However, people sometimes choose the wrong items by mistake, or become frustrated when submenus pop up unnecessarily. This p...
Masatomo Kobayashi, Takeo Igarashi
ASPDAC
2006
ACM
157views Hardware» more  ASPDAC 2006»
15 years 10 months ago
Delay modeling and static timing analysis for MTCMOS circuits
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Naoaki Ohkubo, Kimiyoshi Usami