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» Two efficient methods to reduce power and testing time
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DAC
2008
ACM
16 years 5 months ago
Automatic synthesis of clock gating logic with controlled netlist perturbation
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
Aaron P. Hurst
VISUALIZATION
2003
IEEE
15 years 9 months ago
HyperLIC
Efficient and effective visual presentation of tensor fields is an ongoing research topic in scientific visualization. HyperLIC is a powerful method to visualize 2D and 3D tensor ...
Xiaoqiang Zheng, Alex Pang
TSP
2008
178views more  TSP 2008»
15 years 4 months ago
Monte Carlo Methods for Channel, Phase Noise, and Frequency Offset Estimation With Unknown Noise Variances in OFDM Systems
In this paper, we address the problem of orthogonal frequency-division multiplexing (OFDM) channel estimation in the presence of phase noise (PHN) and carrier frequency offset (CFO...
F. Septier, Yves Delignon, A. Menhaj-Rivenq, Chris...
IJCSA
2008
117views more  IJCSA 2008»
15 years 4 months ago
Altivec Vector Unit Customization for Embedded Systems
Vector extensions for general purpose processors are an efficient feature to address the growing performance demand of multimedia and computer vision applications. Embedded proces...
Tarik Saidani, Joel Falcou, Lionel Lacassagne, Sam...
NLE
2008
140views more  NLE 2008»
15 years 4 months ago
Active learning and logarithmic opinion pools for HPSG parse selection
For complex tasks such as parse selection, the creation of labelled training sets can be extremely costly. Resource-efficient schemes for creating informative labelled material mu...
Jason Baldridge, Miles Osborne