524 search results - page 3 / 105 » Two efficient methods to reduce power and testing time |
AC
2005
Springer
13 years 7 months ago
2005
Springer
Reducing power consumption has become a major challenge in the design and operation of today's computer systems. This chapter describes different techniques addressing this c...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
ATS
2004
IEEE
13 years 11 months ago
2004
IEEE
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
COR
2007
13 years 7 months ago
2007
Minimizing Waiting Time Variance (WTV) is a job scheduling problem where we schedule a batch of n jobs, for servicing on a single resource, in such a way that the variance of thei...
TVLSI
2010
13 years 2 months ago
2010
Abstract--Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requiremen...