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DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 3 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
IPPS
2007
IEEE
14 years 3 months ago
A Comprehensive Analysis of OpenMP Applications on Dual-Core Intel Xeon SMPs
Hybrid chip multithreaded SMPs present new challenges as well as new opportunities to maximize performance. Our intention is to discover the optimal operating configuration of suc...
Ryan E. Grant, Ahmad Afsahi
VTS
2007
IEEE
116views Hardware» more  VTS 2007»
14 years 3 months ago
Case Study: Soft Error Rate Analysis in Storage Systems
Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. In this paper we analyze the soft error vulnerability of FPGAs used in storage systems. Sinc...
Brian Mullins, Hossein Asadi, Mehdi Baradaran Taho...
DATE
2006
IEEE
126views Hardware» more  DATE 2006»
14 years 2 months ago
Analysis and modeling of power grid transmission lines
Power distribution and signal transmission are becoming key limiters for chip performance in nanometer era. These issues can be simultaneously addressed by designing transmission ...
J. Balachandran, Steven Brebels, G. Carchon, T. We...
CODES
2005
IEEE
14 years 2 months ago
Conflict analysis in multiprocess synthesis for optimized system integration
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing arch...
Oliver Bringmann, Wolfgang Rosenstiel, Axel Sieben...