4116 search results - page 140 / 824 » Type Analysis for CHIP |
DAC
2010
ACM
14 years 26 days ago
2010
ACM
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
CODES
2008
IEEE
14 years 3 months ago
2008
IEEE
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
TECS
2008
13 years 8 months ago
2008
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
BMCBI
2005
13 years 8 months ago
2005
Background: A major challenge in computational genomics is the development of methodologies that allow accurate genome-wide prediction of the regulatory targets of a transcription...
DAC
2004
ACM
14 years 10 months ago
2004
ACM
Circuits using nano-meter technologies are becoming increasingly vulnerable to signal interference from multiple noise sources as well as radiation-induced soft errors. One way to...