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» Type Analysis for CHIP
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138
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DATE
1999
IEEE
92views Hardware» more  DATE 1999»
15 years 7 months ago
Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics
Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computation...
Peter Feldmann, Sharad Kapur, David E. Long
126
Voted
POPL
1995
ACM
15 years 6 months ago
A Type System Equivalent to Flow Analysis
Flow-based safety analysis of higher-order languages has been studied by Shivers, and Palsberg and Schwartzbach. Open until now is the problem of finding a type system that accep...
Jens Palsberg, Patrick O'Keefe
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 7 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
124
Voted
ESOP
2001
Springer
15 years 7 months ago
Encoding Intensional Type Analysis
Abstract. Languages for intensional type analysis permit ad-hoc polymorphism, or run-time analysis of types. However, such languages require complex, specialized constructs to supp...
Stephanie Weirich
133
Voted
SDL
2003
147views Hardware» more  SDL 2003»
15 years 4 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...