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» Ultra low power digital signal processing
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DAC
1999
ACM
14 years 1 months ago
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing
We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence i...
Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, J...
CCS
2011
ACM
12 years 9 months ago
On the vulnerability of FPGA bitstream encryption against power analysis attacks: extracting keys from xilinx Virtex-II FPGAs
Over the last two decades FPGAs have become central components for many advanced digital systems, e.g., video signal processing, network routers, data acquisition and military sys...
Amir Moradi, Alessandro Barenghi, Timo Kasper, Chr...
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
14 years 2 months ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
14 years 18 days ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah
ICASSP
2011
IEEE
13 years 23 days ago
Improving kernel-energy trade-offs for machine learning in implantable and wearable biomedical applications
Emerging biomedical sensors and stimulators offer unprecedented modalities for delivering therapy and acquiring physiological signals (e.g., deep brain stimulators). Exploiting th...
Kyong-Ho Lee, Sun-Yuan Kung, Naveen Verma