276 search results - page 6 / 56 » Ultra low power digital signal processing |
IWSOC
2005
IEEE
14 years 17 days ago
2005
IEEE
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...
JCP
2008
13 years 7 months ago
2008
Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper...
ISLPED
2007
ACM
13 years 8 months ago
2007
ACM
To address the productivity bottlenecks in power analysis and optimization of modern systems, we propose to treat power as a signal and leverage the rich set of signal processing ...
ICCAD
1995
IEEE
13 years 10 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
PATMOS
2004
Springer
14 years 10 days ago
2004
Springer
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...