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» Ultra-low power digital subthreshold logic circuits
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CF
2005
ACM
13 years 10 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
14 years 2 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
ISCA
2009
IEEE
159views Hardware» more  ISCA 2009»
14 years 3 months ago
End-to-end register data-flow continuous self-test
While Moore’s Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in t...
Javier Carretero, Pedro Chaparro, Xavier Vera, Jau...
ISQED
2008
IEEE
186views Hardware» more  ISQED 2008»
14 years 3 months ago
Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
Foad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sa...
ISPD
2006
ACM
68views Hardware» more  ISPD 2006»
14 years 2 months ago
Solving hard instances of floorplacement
Physical Design of modern systems on chip is extremely challenging. Such digital integrated circuits often contain tens of millions of logic gates, intellectual property blocks, e...
Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky...