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ISCA
1993
IEEE
157views Hardware» more  ISCA 1993»
15 years 6 months ago
The Performance of Cache-Coherent Ring-based Multiprocessors
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
Luiz André Barroso, Michel Dubois
117
Voted
IEEEPACT
2009
IEEE
15 years 9 months ago
Architecture Support for Improving Bulk Memory Copying and Initialization Performance
—Bulk memory copying and initialization is one of the most ubiquitous operations performed in current computer systems by both user applications and Operating Systems. While many...
Xiaowei Jiang, Yan Solihin, Li Zhao, Ravishankar I...
110
Voted
CIDR
2007
173views Algorithms» more  CIDR 2007»
15 years 4 months ago
Database Servers on Chip Multiprocessors: Limitations and Opportunities
Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, hi...
Nikos Hardavellas, Ippokratis Pandis, Ryan Johnson...
107
Voted
CONCURRENCY
2006
140views more  CONCURRENCY 2006»
15 years 2 months ago
An efficient memory operations optimization technique for vector loops on Itanium 2 processors
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
William Jalby, Christophe Lemuet, Sid Ahmed Ali To...
MICRO
2008
IEEE
124views Hardware» more  MICRO 2008»
15 years 9 months ago
Token tenure: PATCHing token counting using directory-based cache coherence
Traditional coherence protocols present a set of difficult tradeoffs: the reliance of snoopy protocols on broadcast and ordered interconnects limits their scalability, while dire...
Arun Raghavan, Colin Blundell, Milo M. K. Martin