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    ICCAD
    1993
    IEEE
    101views Hardware» more  ICCAD 1993»
    Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits
    15 years 6 months ago
    Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits
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    Kerry S. Lowe, P. Glenn Gulak
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    95
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    DAC
    1993
    ACM
    90views Computer Architecture» more  DAC 1993»
    Optimization of Combinational Logic Circuits Based on Compatible Gates
    15 years 6 months ago
    Optimization of Combinational Logic Circuits Based on Compatible Gates
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    Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni D...
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    DAC
    1992
    ACM
    86views Computer Architecture» more  DAC 1992»
    The Role of Long and Short Paths in Circuit Performance Optimization
    15 years 6 months ago
    The Role of Long and Short Paths in Circuit Performance Optimization
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    Siu-Wing Cheng, Hsi-Chuan Chen, David Hung-Chang D...
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    100
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    DAC
    1992
    ACM
    100views Computer Architecture» more  DAC 1992»
    Recurrence Equations and the Optimization of Synchronous Logic Circuits
    15 years 6 months ago
    Recurrence Equations and the Optimization of Synchronous Logic Circuits
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    Maurizio Damiani, Giovanni De Micheli
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    78
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    ASPDAC
    2007
    ACM
    92views Hardware» more  ASPDAC 2007»
    Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation
    15 years 6 months ago
    Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation
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    Cheoljoo Jeong, Steven M. Nowick
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