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» Understanding POWER multiprocessors
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ISQED
2006
IEEE
101views Hardware» more  ISQED 2006»
14 years 1 months ago
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Oz...
ISLPED
2006
ACM
105views Hardware» more  ISLPED 2006»
14 years 1 months ago
Reducing power through compiler-directed barrier synchronization elimination
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
Mahmut T. Kandemir, Seung Woo Son
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
14 years 18 hour ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
CASES
2003
ACM
14 years 29 days ago
Programming challenges in network processor deployment
Programming multi-processor ASIPs, such as network processors, remains an art due to the wide variety of architectures and due to little support for exploring different implement...
Chidamber Kulkarni, Matthias Gries, Christian Saue...
ECCV
2010
Springer
14 years 14 days ago
Blocks World Revisited: Image Understanding using Qualitative Geometry and Mechanics
Since most current scene understanding approaches operate either on the 2D image or using a surface-based representation, they do not allow reasoning about the physical constrain...
Abhinav Gupta, Alexei A. Efros, Martial Hebert