6 search results - page 1 / 2 » Understanding metrics in logic synthesis for routability enh... |
SLIP
2003
ACM
14 years 3 months ago
2003
ACM
ISPD
2012
ACM
12 years 5 months ago
2012
ACM
There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis ha...
ISQED
2005
IEEE
14 years 3 months ago
2005
IEEE
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
ASPDAC
2005
ACM
13 years 11 months ago
2005
ACM
Incremental physical design is an important methodology towards achieving design closure for high-performance large-scale circuits. Placement tools must accommodate incremental ch...
DATE
2008
IEEE
14 years 4 months ago
2008
IEEE
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...