65 search results - page 8 / 13 » Unified decoder architecture for LDPC turbo codes |
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
RSP
2008
IEEE
14 years 2 months ago
2008
IEEE
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based im...
GLOBECOM
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
FCCM
2008
IEEE
14 years 2 months ago
2008
IEEE
We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
Abstract-- This paper addresses the issue of design of lowrate sparse-graph codes with linear minimum distance in the blocklength. First, we define a necessary condition which need...