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158
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HOTI
2005
IEEE
15 years 10 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
15 years 8 months ago
A portable and extendible testbed for distributed logic simulation
A exible test environment is presented that allows for dierent methods of parallelizing discrete event simulation to be evaluated in a uniform environment. The testbed is portabl...
Peter Luksch
DATE
1999
IEEE
113views Hardware» more  DATE 1999»
15 years 8 months ago
Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
William Fornaciari, Donatella Sciuto, Cristina Sil...
139
Voted
ESA
2008
Springer
159views Algorithms» more  ESA 2008»
15 years 6 months ago
Cache-Oblivious Red-Blue Line Segment Intersection
We present an optimal cache-oblivious algorithm for finding all intersections between a set of non-intersecting red segments and a set of non-intersecting blue segments in the plan...
Lars Arge, Thomas Mølhave, Norbert Zeh
SOFTVIS
2003
ACM
15 years 9 months ago
A New Approach for Visualizing UML Class Diagrams
UML diagrams have become increasingly important in the engineering and reengineering processes for software systems. Of particular interest are UML class diagrams whose purpose is...
Carsten Gutwenger, Michael Jünger, Karsten Kl...