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DAC
2006
ACM
14 years 8 months ago
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil...
DATE
2004
IEEE
146views Hardware» more  DATE 2004»
13 years 11 months ago
Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies
In multimedia and other streaming applications a significant portion of energy is spent on data transfers. Exploiting data reuse opportunities in the application, we can reduce th...
Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nik...
MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
13 years 11 months ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...
EMSOFT
2007
Springer
14 years 1 months ago
Uniformity improving page allocation for flash memory file systems
Flash memory is a storage medium that is becoming more and more popular. Though not yet fully embraced in traditional computing systems, Flash memory is prevalent in embedded syst...
Seungjae Baek, Seongjun Ahn, Jongmoo Choi, Donghee...
SIAMCOMP
2000
66views more  SIAMCOMP 2000»
13 years 7 months ago
Computations of Uniform Recurrence Equations Using Minimal Memory Size
We consider a system of uniform recurrence equations (URE) of dimension one. We show how its computation can be carried out using minimal memory size with several synchronous proc...
Bruno Gaujal, Alain Jean-Marie, Jean Mairesse