326 search results - page 64 / 66 » Usability Engineering in Industrial Practice |
TASE
2011
IEEE
13 years 2 months ago
2011
IEEE
—In this paper, we present a new sketch-based system — KnitSketch, to improve the efficiency of process planning for knitting garments at an early design stage. The KnitSketch...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
ISPD
2009
ACM
14 years 2 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
MI
1993
13 years 8 months ago
1993
AI planning research is now maturing and nding practical application in the commercial, industrial, engineering and defence sectors. This has led to a rapid expansion in the last ...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source – shallow trench isolation –...