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ICASSP
2011
IEEE
12 years 11 months ago
Reconfigurable decoder architectures for Raptor codes
Decoder architectures for architecture-aware Raptor codes having regular message access-and-processing patterns are presented. Raptor codes are a class of concatenated codes compo...
Hady Zeineddine, Mohammad M. Mansour
MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
13 years 6 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
13 years 5 months ago
Frequent value compression in packet-based NoC architectures
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Ju...
HASE
2005
IEEE
14 years 1 months ago
Design and Analysis of Fault Tolerant Architectures by Model Weaving
Aspect-oriented modeling is proposed to design the architecture of fault tolerant systems. Notations are introduced that support the separate and modularized design of functional ...
Péter Domokos, István Majzik
HICSS
2010
IEEE
260views Biometrics» more  HICSS 2010»
14 years 2 months ago
Standardized Device Services - A Design Pattern for Service Oriented Integration of Medical Devices
Service oriented device architecture (SODA) is a promising approach for enabling a continuous IT support of medical processes in hospitals. However, there is a lack of specific de...
Christian Mauro, Ali Sunyaev, Jan Marco Leimeister...