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» Use of statistical timing analysis on real designs
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GLVLSI
2003
IEEE
202views VLSI» more  GLVLSI 2003»
14 years 21 days ago
System level design of real time face recognition architecture based on composite PCA
Design and implementation of a fast parallel architecture based on an improved principal component analysis (PCA) method called Composite PCA suitable for real-time face recogniti...
Rajkiran Gottumukkal, Vijayan K. Asari
ISQED
2009
IEEE
111views Hardware» more  ISQED 2009»
14 years 2 months ago
Efficient statistical analysis of read timing failures in SRAM circuits
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...
Soner Yaldiz, Umut Arslan, Xin Li, Larry T. Pilegg...
DAC
2006
ACM
14 years 8 months ago
A real time budgeting method for module-level-pipelined bus based system using bus scenarios
In designing bus based systems with parallel and pipelined architecture, it is important to derive a real time budget (a specified execution time limit) for each task of a bus bas...
Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Te...
FDL
2006
IEEE
14 years 1 months ago
Reusing Real-Time Systems Design Experience
To ensure correctness and performance of real-time embedded systems, early evaluation of properties is needed. Based on design experience for real-time systems and using the conce...
Oana Florescu, Jeroen Voeten, Marcel Verhoef, Henk...
GLVLSI
2006
IEEE
143views VLSI» more  GLVLSI 2006»
14 years 1 months ago
SACI: statistical static timing analysis of coupled interconnects
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, A...