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DATE
2005
IEEE
108views Hardware» more  DATE 2005»
14 years 2 months ago
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
DATE
2010
IEEE
154views Hardware» more  DATE 2010»
14 years 1 months ago
ERSA: Error Resilient System Architecture for probabilistic applications
There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for...
Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. J...
SLIP
2006
ACM
14 years 2 months ago
The routability of multiprocessor network topologies in FPGAs
A fundamental difference between ASICs and FPGAs is that wires in ASICs are designed such that it matches the requirements of a particular design. Wire parameters such as: length...
Manuel Saldaña, Lesley Shannon, Paul Chow
DSN
2006
IEEE
14 years 2 months ago
Exploring Fault-Tolerant Network-on-Chip Architectures
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
Dongkook Park, Chrysostomos Nicopoulos, Jongman Ki...
ACMICEC
2005
ACM
156views ECommerce» more  ACMICEC 2005»
14 years 2 months ago
Establishing and maintaining compatibility in service oriented business collaboration
Current composite web service development and management solutions, e.g. BPEL, do not cater for assessing and maintaining comparability of business partners during business collab...
Bart Orriëns, Jian Yang