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» Using Decision Diagrams to Design ULMs for FPGAs
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ISQED
2003
IEEE
104views Hardware» more  ISQED 2003»
14 years 24 days ago
Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis
As the portion of coupling capacitance increases in smaller process geometries, accurate coupled noise analysis is becoming more important in current design methodologies. We prop...
Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-...
ICCAD
1999
IEEE
81views Hardware» more  ICCAD 1999»
13 years 12 months ago
Modeling design constraints and biasing in simulation using BDDs
Constraining and input biasing are frequently used techniques in functional verification methodologies based on randomized simulation generation. Constraints confine the simulatio...
Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller,...
PLDI
2004
ACM
14 years 29 days ago
Jedd: a BDD-based relational extension of Java
In this paper we present Jedd, a language extension to Java that supports a convenient way of programming with Binary Decision Diagrams (BDDs). The Jedd language abstracts BDDs as...
Ondrej Lhoták, Laurie J. Hendren
ASPDAC
2007
ACM
152views Hardware» more  ASPDAC 2007»
13 years 11 months ago
A Graph Reduction Approach to Symbolic Circuit Analysis
A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed ...
Guoyong Shi, Weiwei Chen, C.-J. Richard Shi
ICSE
2001
IEEE-ACM
13 years 12 months ago
Effective Software Architecture Design: From Global Analysis to UML Descriptions
It is now generally accepted that separating software architecture into multiple views can help in reducing complexity and in making sound decisions about design trade-offs. Our f...
Robert L. Nord, Daniel J. Paulish, Dilip Soni, Chr...