In this paper, we develop a mixed-size placement tool, Dragon2005, to solve large scale placement problems effectively. A top-down hierarchical approach based on min-cut partition...
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
This paper presents fully parallel domain decomposition (DD) techniques for efficient simulation of large-scale linear circuits such as power grids. DD techniques that use non-ov...
Kai Sun, Quming Zhou, Kartik Mohanram, Danny C. So...
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement...
In this paper, we design recommender systems for weblogs based on the link structure among them. We propose algorithms based on refined random walks and spectral methods. First, w...