643 search results - page 14 / 129 » Using Hardware Counters to Automatically Improve Memory Perf... |
MICRO
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows...
ASPDAC
2000
ACM
14 years 29 days ago
2000
ACM
– This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master cloc...
PODC
2009
ACM
14 years 5 months ago
2009
ACM
The era of parallel computing for the masses is here, but writing correct parallel programs remains far more difficult than writing sequential programs. Aside from a few domains,...
IWMM
2007
Springer
14 years 2 months ago
2007
Springer
Traditionally, operating systems use a coarse approximation of memory accesses to implement memory management algorithms by monitoring page faults or scanning page table entries. ...
ICCAD
2008
IEEE
14 years 5 months ago
2008
IEEE
In this paper we propose an on-chip bus PMU which makes accurate estimates of system power consumption from a first-order linear power model by utilizing system-level activity in...