643 search results - page 55 / 129 » Using Hardware Counters to Automatically Improve Memory Perf... |
ISCA
2006
IEEE
13 years 8 months ago
2006
IEEE
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
ASPDAC
2009
ACM
14 years 3 months ago
2009
ACM
Abstract— In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed instead of caches, which can consume majority of processor power. Howe...
ISCA
2011
IEEE
13 years 3 days ago
2011
IEEE
In this paper we study the impact of sharing memory resources on five Google datacenter applications: a web search engine, bigtable, content analyzer, image stitching, and protoc...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
— Though tag bits in the data caches are vulnerable to transient errors, few effort has been made to reduce their vulnerability. In this paper, we propose to exploit prevalent sa...