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CAV
2008
Springer
157views Hardware» more  CAV 2008»
13 years 8 months ago
Effective Program Verification for Relaxed Memory Models
Program verification for relaxed memory models is hard. The high degree of nondeterminism in such models challenges standard verification techniques. This paper proposes a new veri...
Sebastian Burckhardt, Madanlal Musuvathi
CSREAESA
2004
13 years 8 months ago
Approaches for Monitoring Vectors on Microprocessor Buses
This paper introduces two new methods for observing and recording the vectors that have been asserted on a bus. The first is a software approach that uses a novel data structure s...
Hector Arteaga, Hussain Al-Asaad
ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
14 years 10 days ago
An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays
—This paper presents a memory-conscious mapping methodology of computational intensive applications on coarse-grain reconfigurable arrays. By exploiting the inherent abundant amo...
Michalis D. Galanis, Gregory Dimitroulakos, Consta...
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
13 years 4 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
DATE
2003
IEEE
112views Hardware» more  DATE 2003»
14 years 1 days ago
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula
System design methodology is poised to become the next big enabler for highly sophisticated electronic products. Design verification continues to be a major challenge and simulat...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...